High Speed Counter with Serial Output
This project is an external high-speed counter with serial output, intended for use with a microcontroller that controls the gate time and displays the output.
Most PIC and AVR microcontroller based frequency counters either stop at relatively low frequencies, or incorporate high-speed prescalers built from discrete logic. Since the microcontrollers themselves generally can't count much faster than their own input clock (or a fraction thereof), the output of the prescaler has to be fairly slow.
With a $2 CPLD, the Altera EPM3064A, we can create a wide, high-speed counter with a serial output. A microcontroller (which can now run at any clock rate, conserving power) drives the control lines and then clocks out the counter value after each gate time. When it's not counting, the quiescent current is almost nothing, and it's available in small, but fairly hobbiest-friendly packages like TQFP. Since you'll only need a few pins connected, you can even prototype it dead-bug style.
By avoiding a prescaler altogether, the counter can be accurate to 1Hz even with a 1s gate time. The CPLD also drives a signal that lets you synchronize the gate timer to edges on the input signal, allowing you to measure periods for low-speed input. With a precisely timed "blind" gate time, the counter is accurate to 1 part in the input clock domain. With the gate time synchronized to the input edges, the error is limited to 1 part in the timebase.
Software and Hardware
Download the Quartus II Web Edition from Altera (that URL will probably change as they release new versions). You'll need to build or buy a Byteblaster II or Byteblaster MV style cable. This is just a 74HC244 tri-state buffer on a parallel port. There are schematics in Altera's documentation.
Verilog Source
The verilog source is very simple. There's a comment at the top explaining how to drive it. If you build this project yourself, remember to use the pin assignments tool to put RST on "global clear" and CLK on "global clock". The serial data clock, SCLK, can go anywhere, since it's only being driven at low speed. Then make sure CLK and SCLK are marked as "clocks" to avoid warnings in the tool.
Programming File
If you just want to buy the exact chip, here's a bit file for an EPM3064ATC44-4. That's a 44TQFP. The pin assignments are:
| clk | 37 (global clock) |
| rst | 39 (global clear) |
| ce | 2 |
| counting | 3 |
| sclk | 5 |
| sdata | 6 |
The counter is 28 bits wide, so it can count to 268435456. Read 28 bits of output, LSB first, and the LSB is available immediately after CE goes low and before the first time you strobe SCLK. The timing analyzer says 208MHz, but it can likely count at 300MHz+